Student Perceptions of Programming Instruction in a Makerspace vs Synchronous Remote Environment

All first-year students at the J. B. Speed School of Engineering (SSoE) at the University of Louisville (UofL) are required to complete a two-course sequence. The purpose of the two-course sequence is to introduce incoming students to the fundamentals and profession of engineering. The first course in the sequence is titled Engineering Methods, Tools, & Practice I (ENGR 110) and primarily focuses on introduction to and practice with fundamental engineering skills. The second course Engineering Methods, Tools, & Practice II (ENGR 111) is a makerspace-based course primarily focused on application and integration of the fundamentals learned in ENGR 110. ENGR 111 includes a variety of fundamental skills in its instruction, one of which is programming. Therefore, all disciplines of SSoE engineering students are exposed to the basics and applications of programming through this course sequence. Programming instruction in ENGR 111 is designed to include relevant software development skills that students might encounter in the engineering profession. The students have learned initial programming skills in their ENGR 110 course through the Python programming language. In ENGR 111, students practice programming skills learned in ENGR 110 on two different platforms: Arduino Microcontrollers (Arduino) and Programmable Logic Controllers (PLCs). In normal face-to-face semesters, students are put into teams of 3 to 4 and given modules to develop and practice these skills (two for Arduino, two for PLCs). Due to the COVID-19 pandemic, ENGR 111 was augmented into a synchronous remote course to avoid close proximity and shared tools in the makerspace. Arduino programming instruction was performed using Tinkercad (tinkercad.com), a website that allows for Arduino programming and circuitry simulations. PLC instruction was performed utilizing a free online PLC simulator website, “PLCfiddle” [1]. At the end of each semester, students take a survey on their perceptions of the course. Included in this survey are questions pertaining to programming instruction. These questions assess student confidence in programming and platform preference. Results of these questions from Spring 2019 (a makerspace iteration) and Spring 2021 (a remote iteration) are compared in this paper. © American Society for Engineering Education, 2022.

A Novel Project-Oriented System on Chip (SoC) Design Course for Computer and Electrical Engineers

This paper describes a novel project-oriented system on chip (SoC) design course. The course is taught in the Computer Science and Engineering (CSE) Department at the University of Texas at Arlington and is offered as CSE 4356 System on Chip Design for computer engineering undergraduates, as CSE 5356 for computer engineering graduate students, and as EE 5315 for electrical engineering graduate students. It is taught as one course combining all numbers. All students are given the same lectures, course materials, assignments, and projects. Grading standards and expectations are the same for all students as well. The course in its current form was first offered in fall 2020 and was taught online due to COVID-19 restrictions. The course was offered again in fall 2021 in a traditional on-campus, in-person mode of delivery. Two seasoned educators, with more than eighty years of total teaching experience, combined to team teach the course. One also brought more than thirty years of industrial design experience to the course. SoC FPGA devices have been available for use by designers for more than 10 years and are widely used in applications that require both an embedded microcomputer and FPGA-based logic for real-time computationally-intense solutions. Such solutions require skills in C programming, HDL programming, bus topologies forming the bridge between FPGA fabric and the microprocessor space, Linux operating systems and virtualization, and kernel device driver development. The breadth of the skills that were conveyed to students necessitated a team teaching approach to leverage the diverse background of the instructors. With such a wide range of topics, one of the biggest challenges was developing a course that was approachable for a greatly varied population of students - a mix of Computer Engineering (CpE) and Electrical Engineering (EE) students at both the graduate and undergraduate level. Another, perhaps less obvious, challenge was the inherently application focus of the course, which presents challenges to many graduate students whose undergraduate degree lacked a robust hands-on design experience. Selection of an appropriate project was key to making the course effective and providing a fun learning experience for students. The projects were aligned to relevant industry applications, stressing complex modern intellectual property (IP) work flows, while still being approachable to students. The design of a universal asynchronous receiver transmitter (UART) IP module in 2020 and a serial peripheral interface (SPI) IP module in 2021 were chosen as the projects for the first two offerings of the course. The Terasic/Intel DE1-SoC development board and Intel Quartus Prime 18.1 design software were the technologies chosen for the course. The development board and basic test instruments were provided to each student in a take-home lab kit. The system on chip design course has proven to be a popular but challenging course for our undergraduate and graduate students in computer engineering and electrical engineering. The course has demonstrated that it is possible to successfully teach an advanced design-oriented course to students of varying majors, levels, educational backgrounds, and cultures. © American Society for Engineering Education, 2022.

Distance Learning of Programmable Logic Control: An Implementation Example

This article describes the implementation of a distance learning course in programmable logic control designed and delivered during the Covid 19 pandemic. The course has a strong practical orientation, so it was a particular challenge to maintain this orientation in the remote implementation of the course. The goal was achieved through a combination of software simulation tools, remote access to computers in the lab and interactive sessions with an instructor. © 2022 IEEE.

VVC intra prediction decoder: Feature improvement and performance analysis

Nowadays, streaming applications have been in great demand, especially due to covid-19 (teleworking, online teaching, virtual reality, etc.). In addition, artificial intelligence has become widely used especially in video processing domains, so a video with high quality improves the accuracy rate of this application. To meet these needs, the Versatile Video Coding standard (VVC) has appeared to give a high compression efficiency compared to high-efficiency video coding. This norm consists of a high complexity algorithm that offers an improvement in processing time and decreases the bit rate by 50 % thanks to several new compression techniques. In this context, we propose the implementation of an intra prediction decoding chain of this standard on a system on chip. In this work, we highlight the VVC feature enhancements, we present the suitable method for VVC intra-prediction decoder implementation on the PYNQ-Z2, and we provide profiling in terms of decoding time and power consumption. As a future work, this study is helpful to distinguish the block that will be a candidate for a Hardware acceleration. © 2022 IEEE.

Implementation of an Embedded Masked Face Recognition System using Huskylens System-On-Chip Module

Globally, Facial recognition systems have been increasingly adopted, by governments, as a viable means of identification and verification in public spaces such as the airport, train stations, and stadiums. However, in the wake of the COVID-19 outbreak, the World Health Organization (WHO) declared that wearing face masks is an essential safety precaution. As a result, current facial recognition systems have difficulties recognizing faces accurately, which motivated this study. This research aims to implement an embedded masked face recognition system using the HuskyLens SoC module to identify people, even while wearing a face mask. The developed method was actualized using the Kendryte K210 chip embedded in the HuskyLens module. This system-on-chip design was integrated with other peripherals using an Arduino Pro-mini board. The results of testing and evaluating the system's performance show that the system's facial recognition accuracy with masked and without masks faces was 90% and 95%, respectively. Implementing this solution in our environment would enable accurate real-time recognition of masked and unmasked faces © 2022 IEEE.

An Effective approach for implementing COVID-19 CT Lung Segmentation using Low-Cost System on Chip

Computer vision techniques always had played a salient role in numerous medical fields, especially in image diagnosis. Amidst a global pandemic situation, one of the archetypal methods assisting healthcare professionals in diagnosing various types of lung cancers, heart diseases, and COVID-19 infection is the Computed Tomography (CT) medical imaging technique. Segmentation of Lung and Infection with high accuracy in COVID-19 CT scans can play a vital role in the prognosis and diagnosis of a mass population of infected patients. Most of the existing works are predominately based on large private data sets that are practically impossible to obtain during a pandemic situation. Moreover, it is difficult to compare the segmentation methods as the data set are obtained in various geographical areas and developed and implemented in different environments. To help the current global pandemic situation, we are proposing a highly data-efficient method that gets trained on 20 expert annotated COVID-19 cases. To increase the efficiency rate further, the proposed model has been implemented on NVIDIA-Jetson Nano (System-on-Chip) to completely exploit the GPU performance for a medical application machine learning module. To compare the results, we tested the performance with conventional U-Net architecture and calculated the performance metrics. The proposed state-of-art method proves better than the conventional architecture delivering a Dice Similarity Coefficient of 99%. © 2021 IEEE.